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Multi chipdesign (4-6-8)  with AD9361

Question asked by Constantine on Mar 9, 2016
Latest reply on Mar 9, 2016 by tlili

Hello,

 

We want to launch MIMO 8x8 with AD9361 chips, but now have some questions

 

We're going to use FMCOMMS5+ZC706 kit. Recieve and trancieve data via 1G ethernet. One board works Ok, but what about two boards? Three boards?

 

Now I can the next problems

1) On FMCOMMS5 ADC/DAC in both chips  work strongy synchronus. So If we would use two FMCOMMS5 boards, we must use some external trigger singal- connect two boards with SMA cable, so we can load data into both boards and launch DAC (or ADC capture) strongly in the same moment? Is it possible?

 

2) The next problem - FPGA PLL. As I see FPGA gives clock to AD9361 chips, so we must use external LO for FPGAs or try to synchronize both PLL one to another?

 

3) And the last one is RF band sync. The easises way may be use external LO, but maximum possivle RF frequency is 4GHz, it's too low for us. So we must use internal LO in all chips, select one chip as Master and sync 3 other slaves to it?

Synchronizing multiple AD9361 devices [Analog Devices Wiki]

So we need some external board with RF swithcers, controlled from FPGA, to switch Master TX to different RX chips?

 

Thank you in advance

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