I am having powerup issues with the internal LDOs (AD7124-8 pins 1 and 24). The problem is pin1 is at about 1V and pin24 is at about 0.2V. The chip does not seem to be pulling excessive current. This seems to be intermittent; every once in a while it will work. This is happening on all three of the engineering boards.
IOVDD = 3.3V
AVDD = 1.8V
AVSS = -1.8V
REFOUT = NC
REFIN1+ = NC
REFIN1- = NC
CLK = NC
SYNC = 3.3V
After writing this I am a bit concerned about how I connected the AINX lines. I have 6 lines connected to opamps via 10k res. These opamps are powered from +/-12V. The 3.3V and +/-1.8V are derived from the +/-12V. Is is possible for the ADC to get latched up when a opamp rails and the bias power is not up yet? Also is there a powerup sequence I am violating? I did not see a powerup sequence spec in the datasheet.
Here is the sw side:
The spi setup that gets the ball out of our court:
- Power-up or Micro-Controller Reset
- Transmit 64 consecutive 1s to AD7124 to software reset.
- Set control register to 0x15C8 by sending 0x0115C8
- Read AD7124 Id register to verify valid spi communication by sending 0x4500 and verifying that the last byte of MISO data is 0x12
When the bus is working, this setup works great. When the bus fails, we read back all 0's.
The remainder of the setup is about 40B of write and 10B of readback limited to the Config, Filter, Channel, Error Enable, and Error registers.
We use the error enable register to enable spi CRC check-sums on both master write and slave read, and under normal circumstances the CRC check-sums in both directions are valid. When the AD7124 fails the data is all 0's or all 1's and our check-sums don't pass.