I get the project no-OS-2014_R2 from internet. Are there some documents of the files:axi_ad9361_tx_channel.v, axi_ad9361_tx.v, axi_ad9361_rx_channel.v and axi_ad9361_rx.v in library/axi_ad9361. If yes, where can I find them?
I can only tell you the functions of the IQ correction module,as it's implemented in HDL:
iq correction = a*(i+x) + b*(q+y); offsets are added in dcfilter (for the ADC Path)
You could create your own module which implements the desired function.
Please do not create multiple topics with the same problem.
Please see: ADI Reference Designs HDL User Guide [Analog Devices Wiki]
In case this does not answer your question let us know.
Thank you for your reply. I still can not find the description of the code in these files.
the axi_ad9361 receives data from four ports(dac_data_i0[15:0],dac_data_q0[15:0],dac_data_i1[15:0]
and dac_data_q1[15:0])and sends data through two ports(tx_data_out_p[5:0]and tx_data_out_n[5:0]). I want to know how data are processed in the axi_ad9361 core? Can you tell me where I can find the document?
Moving to Microcontroller no-OS drivers.
Moved to FPGA Reference Designs.
There is no explicit description of the code in those modules other than the code itself.
Regarding how the data is processed, for the ADC path for example, it depends on the ADC Common and ADC Channel registers : ADI Reference Designs HDL User Guide [Analog Devices Wiki]
Same for the DAC path.
Thank you for your reply. when we use the function dac_init(ad9361_phy, DATA_SEL_DMA); and how the data is processed. do it just take the 12 MSBs?
Yes, the 12 MSBs from the data that comes on the dac_data ports is used.
Thank you for your reply. Before the data transmitted through adc_data_i0[15:0](adc_data_q0[15:0]...), why does it take a i/q correction action?
Please check https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/iq_correction
Thank you for your reply. I have some more questions.
1. Is it the same reason that apply I/Q correction to the data received through dac_data ports(dac_data_i0[15:0], dac_data_q0[15:0]...)? To get the perfect I/Q signals before up-converter? why does it not need to take action to remove DC bias?
2. I have seen a equation in the web page you mentioned, below is the equation:
what is the relationship between the value of register REG_CHAN_CNTRL_8( Base (common to all cores) [Analog Devices Wiki]) and A, C ,D? for example, when it sets register REG_CHAN_CNTRL_8 to 0x00004000, what is the value of A, C and D?
Can you still see me?
On the DAC side, the data that is sent from memory can be generated without DC offset. Altough it IQ correction on the DAC is available in the HDL, I don't think it is used in the design when streaming data from the memory.
Thank you for your reply. I have understand the DAC side if the IQ correction is not used.
But I still have confusions about the set of the matrix parameters A, C ,D. I also have expressed my confusion in the reply of the topic the function of removal filter in project no-OS-2014_R2.
Can you tell me how to set the matrix parameters A,C,D?
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