AnsweredAssumed Answered

AD9250 Subclass 1 LMFC offset resets jesd output data

Question asked by sam_thales_uk on Mar 8, 2016
Latest reply on Apr 21, 2016 by J.Harris

Hello,

 

I'm currently trying to interface the jesd204b on the AD9250 with an Arria V SOC FPGA.

 

The jesd204b serial interface is working fine on subclass 0, and I can see the correct digital data coming though.

 

The problems comes when I use subclass 1. I'm sending a periodic sysref to the ADC and FPGA. I'm writing 0x1 and 0x3 to register 0x3A like on the datasheet. If I do only this I don't get any data coming though. The only way I get data through is if I write 0x8 or 0xA or 0xC or 0xE to register 0x8B.


The issue then is the digital output I get from the ADC. I get the correct data but every time after some samples, the ADC stops outputing data for a couple of hundreds of clock cycles and then starts outputing correct data and then stop again.... I've attached a screenshot of the output to show.

 

Why is it doing that ? How can I solve this problem ?

 

Thanks in advance


Samlane.JPG

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