I set up 3 ADF7023 chips, one as transmitter at 915 MHz, one as receiver at 915 MHz, and one as tunable jammer.
I set them up for 70 KHz deviation gfsk, 200 kbps. I then run the packet error test (4000 packets), figure out the threshold power level, and set up the transmitter to send to the receiver at 10 dB above the threshold level (i.e. with no packet errors).
I then set up the 3rd board as a tunable jammer. I tell it to continuously transmit the preamble (acting a little like a continuous jammer). I then vary the center frequency of the jammer, either above 915 mhz (highside jammer) or below 915 MHz (lowside jammer). I select a jammer frequency, run the PER test transmit to receiver, and increase the jammer power until I see a 5% PER rate.
I get the following data:
Spacing [KHz] Jammer/Signal allowed
430 26.7 dB
514 36.9 dB
535 38.8 dB
639 44.1 dB
800 47.5 dB
430 17.5 dB
514 14.8 dB
535 14.5 dB
639 16.3 dB
800 19.0 dB
example: Highside "430 KHz" means the jammer is sending its preamble continuously and is centered at 915.430 MHz, while the transmitter is sending PER test at 915.000 MHz. The jammer is causing a 5% packet error rate when its power is 26.7 dB above the desired signal being transmitted.
MY QUESTION: Why does the ADF7023 handle highside jammers much better than lowside jammers? What is going on, either RF, IF, or DSP processing in the chip, to cause this differrence in performance? Alisasing? IF Harmonics?
Since in my application I am equally likely to have either high or low side jammers, is there something I can do (vary data rate slightly, etc) to more balance out the higside/lowside IF filtering of the jammer signal???