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AD9364 suspect initialization state

Question asked by pete_harbour on Mar 7, 2016
Latest reply on Apr 18, 2016 by pete_harbour

Hi,

 

I am running a AD9364 eval board (FMCOMMS4) on an Altera SoC system with the 01-11-2016 no-OS driver.  I have configured the board for standard LTE 30.72 Msps operation and have debug messages on.  This setup does not have the full Altera SoC FPGA implemented and ad9361_dig_tune does not succeed as such.  I am seeing indications that the synthesizers are not successfully configuring on the 1st attempt on a specific HW platform (SoC system).  On other SoC systems I do see the synthesizers configure correctly on the 1st attempt.  My goal is to understand the likely issue that is causing improper synthesizer initialization.  I have attached a print of the debug messages during initialization.  An excerpt of the initialization process is listed here in-line...

 

ad9361_rfpll_int_round_rate: Rate 1797500000 Hz

ad9361_rfpll_int_set_rate: Rate 1797500000 Hz Parent Rate 80000000 Hz

ad9361_fastlock_prepare: TX Profile 0: Un-Prepare

ad9361_rfpll_vco_init : vco_freq 7190000000 : ref_clk 80000000 : range 2

ad9361_rfpll_vco_init : freq 7135 MHz : index 32

ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_int_recalc_rate: Parent Rate 20000000 Hz

ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_int_recalc_rate: Parent Rate 20000000 Hz

ad9361_rfpll_int_recalc_rate: Parent Rate 80000000 Hz

ad9361_clk_mux_set_parent: index 0

Device is in 4 state, forcing to 5

ad9361_trx_ext_lo_control : RX state 0

Could not restore to 4 ENSM state

ad9361_clk_mux_set_parent: index 0

Device is in 4 state, forcing to 5

ad9361_trx_ext_lo_control : TX state 0

Could not restore to 4 ENSM state

ad9361_load_mixer_gm_subtable

 

 

Any advice as to the nature of what is not operating properly would be well appreciated.

 

 

Thanks in advance,

 

Pete

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