acutally im sure this topic is better related in a xilinx forum (which is already posted, there but without any respone), but maybe you can help me out.
we are working on a custom Board design related to the ZedBoard. The length of data line etc. are different to the zedboard design and therefore i thought we need to change the DDR timing constraints in zynq hardware design (http://www.xilinx.com/support/answers/46778.html). Running the SDK DRAM Test shows that there are many errors, which is weird regarding to our clear calculation.
To analyze how the impact of changing the delays in hardware design is, we set the all delays for the zedboard reference design to zero and generated the outpout again to programm the zedboard zynq ps.
After building the design and configured the PS, we started a simple hello world application without any error. Moreover we startet the DRAM test and Memory Test application from SDK to see how the delay-change will impact the zedboard ddr config.
The really weird thing is, that nothing seems to be gone bad. All test were passed and there seems no real impact of changing the delays or trance length for the zedboard desgin. May it possible that something went wrong in vivado, that the new delay were not been used?
We did the following steps
1) Changed the Zynq PS config and saved them.
2) Synthesis, Implementation, Generating Bitstream
3) Export Hardware
4) Launch SDK
5) Build a new application with the generated "system_top_hw_platform_1" from vivado and used the example DRAM Test
6) Programm the PS (and PL) via JTAG through SDK
7) Run the Programm and saw that just the short test failed with the given prompt:
How is this even possible?? (by the way: DRAM Training were enabled)
Thanks and regards