My application requires 1 SPDIF inputs, 8 analog inputs and 8 analog outputs. ADC/DSP is master clock. SPDIF use ASRC.
Such applications are very common like ADAU145x.
1. How much work is required to complete such a modification?
For a person who is not familiar with, this can be done?
2. After the modification of the existing system design will have any effect?
For example, the memory size and address need to change in the IC control windows?