i have a few questions about get this part to work right.
my criteria on this part is as follows.
1. sample rate is 48khz
2. i want to use this part in TDM4 mode - 4channels (slots) in a TDM frame, 24bits/slot so the BLCK freq is 4 X 24 X 48khz = 4.608Mhz
3. i want to use this part in slave mode.
4. i want to use pll.
a. if i want to use MCLKI pll, there is no entry in MCS of PLL_CONTROL register for 96 x fs, then do i have to feed 384xfs = 18.432Mhz into this part?
b. if i want to use LRCLK pll, then to get this part to work, i don't need to program MCS of PLL_CONTROL register and only set SAI_CTRL0 , SAI_CTRL1 to proper settings, then will i get the pll working right as intended?
thank you in advance.