I've seen the ADI article on receiving ADS-B signals as well as worked thru an example of using the BSP's you made for HDL Workflow Advisor - excellent work and thank you for creating this high level abstraction workflow.
For those of you wondering what I'm talking about, this Workflow means you don't need to get involved with any of the FPGA tools or RTL. You simply create your DSP functionality in a Simulink design, then within HDL Coder you press the magic "GO" button and it all gets implemented inside the Xilinx FPGA (a new IPcore is created and inserted in the data path within the ADI HDL reference design, then all the Xilinx tools are run automatically in the background to create a new bitstream)..
My question - within the BSP functionality you've implemented either a "Receiver data path BSP" OR a "Transmitter data path BSP". My application requires both Rx and Tx i.e. I receive a signal, modify/manipulate it within the FPGA then re-transmit it. Is there a reason why you implemented the BSP for Matlab as two separate Rx and Tx options? Is it because there are only 3 HP AXI Stream interfaces?
I don't think there's any reason why we can't have both Rx and Tx data flows in the same BSP but you may be able to tell me different.