How do I increase the frequency in the Rx clock chain to use more decimation and allow the max number of FIR filter taps to increase? I'm using a sample rate of 6 M and the clock chain computed will only allow 64 taps. Any advice?
you need to load a filter that specifies 4x interpolation/decimation.
See here: AD9361 high performance, highly integrated RF Agile Transceiver™ Linux device driver [Analog Devices Wiki]
To test load the GSM filter then enable it and afterwards set you baseband rate to 6MSPS.
6 * 4 * 2 * 2 * 2 = ADCCLK = 192 MHz
That should allow you to use 128 TAPS.
These are the constraints on number of taps for Rx FIR.
coef RAM: No more than 128 taps
data RAM: No more than 64 taps unless the RFIR decimation is 2 or more.
ADC CLK : if CLKADC < 300 MHz, no more than 16·(CLK_ADC/CLK_OUT).
if CLKADC > 300 MHz, no more than 16·(½·CLK_ADC/CLK_OUT)
how do I get to 128?
what calls do i do?
First of all thanks for all your help. It is greatly appreciated.
An example of a call would be:
rval = ad9361_set_rx_sampling_freq(ad9361_phy, value);
where ad9361_phy is your structures of various parameters and value = 6000000.
This function calculates a clock chain. How do I get a clock chain value to allow me to use a FIR filter with 128 taps.
The equation is
tap_max = ((ad9361_phy->pdata->rx_path_clks[ADC_FREQ] / ((ad9361_phy->pdata->rx_path_clks[ADC_FREQ] == ad9361_phy->pdata->rx_path_clks[R2_FREQ]) ? 1 : 2)) / ad9361_phy->pdata->rx_path_clks[RX_SAMPL_FREQ]) * 16;
Moving to Linux Software Drivers.
What environment are you using? Linux or bare metal/no-os?
You have seen the filter wizard? That will help you make sure you have all the settings for the various half bands, so you can use 128 taps (if you want).
Suggestion would be to use the filter wizard, and then load this up - these will set things properly.
Robin What about the clock chain calculations. How is the ADC clock calculated. That seems to be the one that controls the number of taps that are allowed. I perform the set sample frequency call and the ADC clock comes back with a frequency of 48,000,000 for a 6,000,000 sampling frequency. This ADC frequency allows only 64 taps when the algorithm in the function ad9361_validate_enable_fir (...) is applied. If I can get the ADC clock rate to 96,000,000, then I can use 128 taps. How, via the driver to you get this clock rate to increase? Do I need to set a parameter(s) in the ad9361_rf_phy structure to set decimations and to control clock chain frequencies? Thanks for the help RJ
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