I would like to use HMC703 to build up a PLL with a VCO which provides a very low input frequency of 2.3MHz.
I use the HMC703 Eval Board and simulated the loop filter with ADIsimPLL. In the simulation the PLL locks but in reality not.
To find the mistake I connected a signal generator instead of the VCO to the RF input of the PLL. I tried two different input frequencies of on the one hand 50MHz and on the other Hand 70MHz.
On the oscilloscope I look at the PLL output of Pin 5 LD_SDO. I configured the PLL in that way that the by 100 divided RF input signal is on that Pin (10:vdiv pfd) (See attached sceenshot).
When the Input signal is 50 MHz the divided signal seems not correct. I expected a frequency of 500 kHz. Compared to the 50 MHz input signal, the 70 MHz Input signal works correct. The frequency of the Peaks is as expected 700 kHz (See attached sceenshot).
Does somebody has any idea what I have to consider when I have RF Input frequencies below 50MHz?