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ADuC7023: Problem with Timer 0 interrupts when using 32kHz clock source

Question asked by MikeL Employee on Jul 1, 2011
Latest reply on Jul 1, 2011 by MikeL

Timer0 doesn’t work correctly when the internal 32.768kHz osc is selected as clock source.

 

This issue doesn’t occur when using HCLK.

An interrupt is expected every 24ms. But interrupts occur every 5uS  happens at “RST_L Timer interrupt ” routine below.

 

 

[DEFINE]

#define T0_COUNT 49 // 1000000/(32768/16)=488.28125us, 24ms = 49(23.926ms)

 

[TIMER0 start up]

T0LD = T0_COUNT;                // Counter Value

T0CON = 0x00E4;         // Periodic,Internal,1/16

IRQEN |= RTOS_TIMER_BIT;        // Enable Timer0 IRQ

 

[interrupt routine]

int_status = IRQSTA & IRQEN;

//---------------------------------------------------------------

// Watchdog Timer interrupt

if(int_status & WATCHDOG_TIMER_BIT){

        drv_watchdoc_int();

}

//---------------------------------------------------------------

// RST_L Timer interrupt

if(int_status & RTOS_TIMER_BIT){

        drv_t0_rstl_int();

        T0CLRI = 0xFF;                          // Clear current timer Interrupt

}

//---------------------------------------------------------------

// Timer interrupt

if(int_status & GP_TIMER_BIT){

        drv_t1_elp_int();

        T1CLRI = 0xFF;                          // Clear current timer Interrupt

}

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