I'm using the reference design FMCMOTCON2.
In the block design of the reference design, the input port GPIO_I[63:0] of the block "sys_ps7" is a 64-bit signal. But after the synthesis, the name of this input port is changed to be "gpio_bd" and it now has only 32 bits. How can we explain it?
I'm going to use a part of this GPIO input port, for example, eight switches and five push buttons on the Zedboard. So I'd like to know which number of bits of this input port should be set to, while using a Gateway_In block in the Xilinx System Generator?