We are having trouble programming the device reliably. Initially we had no control over the device but now we have been successfully able to program the device but we have had instances whereby the device appears to be locked up and we have to power cycle our product to get it to work. We are suspicious that conditions from power up maybe the issue, in our scenario Power to the device is applied then a short time later LE and CLK transition high which is the default power up state of the FPGA pins that are controlling the device. Once the FPGA is loaded the CLK transitions low and he signals stay in this state until a write happens. As far as timing goes i believe we meet the conditions of the data sheet as shown:
So my question is are there any conditions you are aware of that can cause the device to get into a faulty locked up state or are there any other considerations we should be mindful of?