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ADuCM36x DAC interpolation mode performance

Question asked by rbaml on Mar 1, 2016
Latest reply on Mar 8, 2016 by ABuda

I'd be grateful for some help understanding the performance of the DAC when used in 16 bit mode...

 

1) Do I understand correctly, that when used in 16 bit mode, the DAC dithers between two output values, in order to achieve the additional bits, and that in that mode, since the DAC settling time is 10uS, and the maximum DAC interpolation clock divider is 32, that this limits UCLK to 1/(10uS / 32) = 3.2MHz?, and the rate at which the DAC voltage can be updated to 2 * 10uS = 50KHz

 

2) The datasheet mentions that in 16bit mode, only 14 effective bits are achieved. Is it that literally, although the interpolation should result in 16 bits on paper, for whatever reason only 14 bits worth of monotonic output is achieved?

 

Thanks for any help,

 

Ross

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