I'd be grateful for some help understanding the performance of the DAC when used in 16 bit mode...

1) Do I understand correctly, that when used in 16 bit mode, the DAC dithers between two output values, in order to achieve the additional bits, and that in that mode, since the DAC settling time is 10uS, and the maximum DAC interpolation clock divider is 32, that this limits UCLK to 1/(10uS / 32) = 3.2MHz?, and the rate at which the DAC voltage can be updated to 2 * 10uS = 50KHz

2) The datasheet mentions that in 16bit mode, only 14 effective bits are achieved. Is it that literally, although the interpolation should result in 16 bits on paper, for whatever reason only 14 bits worth of monotonic output is achieved?

Thanks for any help,

Ross

Hi Ross,

I'll answer your second question and come back later to the first one.

2) Yes that's correct. Only 14 bits of monotonic output can be achieved. Even though there are 16 bits available when the dithering is used in interpolation mode it's not accurate enough to give you the full 16 bits monotonicity and only 14 can be achieved.

1) Your understanding is correct with regards to the dithering. Your figures appear correct at a glance, however I need to spend a bit of time to look up the numbers and ensure that everything is correct

Regards,

Alex