I didn´t found the information of the Vtune Voltage Range in the datasheet of the HMC1033.
I suppose it´s 0-3.3V but I wanted to be sure.
Thanks in advance!
Correct. The HMC1033 is a single 3.3V rail integrated PLLVCO.
Usually the CP output is connected through a passive loop filter back to Vtune. For these designs the voltage on Vtune is constrained by the 0 to 3.3V CP output. You could design an active loop filter with Vtune driven from an op-amp but there is no advantage over a passive circuit. The op-amp adds noise and complexity.
Thanks for the information.
As I´m using the HMC1033 only as VCO, this question came along.
The "VCO" in the HMC1033 is actually four separate switched capacitor VCO's. The design is similar to the HMC832 design shown below:
Set VCO_register 0x00[8:7] to select one of the four VCOs. Select VCO_register 0x00[6:1] to set the associated switch capacitor setting. Your application will work fine. Just be aware there is some setup required to configure the VCO subsystem for your desired frequency.
Thanks for the info. It´s interesting that the 2 Bits [8:7] are selecting the VCO´s, I didn´t know that.
The device works really good after I figured out the indirect Register addressing of the VCO.
I´m using the VCO between 60-180MHz, in my application I only need to be able to tune the VCO a few MHz after selecting the initial frequency. The phase detector is in my FPGA, along with the prescalers.
The PLL with my FPGA and the HMC is working just fine, i´m now searching for the setting that gives me the widest tuning range for the VCO. As far as i´ve seen the Tuning Range changes with the divider settings an can Range from 3.4MHz to 0.4MHz. For the application 2-4MHz should be enough.
As i´ve seen in my measurements it´s possible to make slight adjustments to the capacitor settings while the PLL is locked without losing lock. So I should be able to keep the Vtune in the middle of the tunable range by shifting it with the capacitor settings, before it get´s to close to the borders .
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