From the Datasheet I found out that the ADC in the AD9361 is a third-order sigma-delta ADC with nine states. Can anybody tell me how I can calculate the actual sampling rate of the 9-state digitizer in the sigma delta ADC?

I run my PLL at 768 MHz. The ADC sampling rate is 48 MHz but as far as I understand this is the sample rate after the sigma-delta downsampling (so with 12-bit resolution) and not the sample rate of the actual 9-state digitizer.

Thank you for the help

Oliver

I think that you have a configuration similar to the one shown below:

The ADC is clocked at 48MHz and its output data rate is 48MHz.

We can not provide more detail on the internal ADC operation.