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Inserting user logic in the FMCADC2 reference design

Question asked by esiee-elt on Feb 26, 2016
Latest reply on Feb 26, 2016 by rejeesh

Hi there!


In a previous topic ("Processing and sending data using the FMCADC2") we asked for directions on what would be the most appropriate place to put a logic to process data from an AD9625 board "on-the-fly" (FMCADC2 board), and following your advice, we developed our own code to do it before sending it to the FIFO, as you can see in the images below, one with the original design and the other with our modifications (the block marked "MY LOGIC").







As we want to be sure that our code will most probably work, before asking for a JESD 204 evaluation license which is available for only 7 days, we would like to check with you whether our arrangement for the signals are OK. Specifically, we are using the signals adc_clk, adc_enable and adc_data[255:0] with the following assumptions:

  - adc_clk runs at the ADC sample rate (at present, that's 2.5 GHz or 0.4ns period, but we intend to drop this to 1GHz);

  - adc_enable is at logic level '1' for one period of adc_clk, when there's data available for storing in the FIFO;

  - adc_data has 32 samples from the AD converter, 8 bits each, 256 bits total.


So, adc_enable occurs every 32 adc_clk cycles. Are these assumptions correct?


On the output side, our logic consumes eight blocks of 32 ADC samples (eight blocks with the full 256 bits collected between two adc_enable signals), and produces one single 256 bits block at adc_wdata, activating the signal adc_wr for a single adc_clk period. According to our calculations, 32 samples taken at the 2.5 GHz rate occur every 12.8 ns, and we produce our own 256 bits of data at adc_wdata every 102.4 ns, keeping the byte to bit rate (both at 2.5 samples/s).


What we want is to acquire data, process it and store this processed data. By doing so, our original 2.5GS/s drops to 313 MS/s, since for every 8-bit sample from the ADC we produce a single bit. Likewise, for every 8 x 32 samples from the ADC, we produce 256 bits.


Our logic has been simulated, and is validated assuming the signals as stated. We would like to hear from you whether our assumptions are correct and for suggestions if not.




Gustavo Fonseca.