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Phase noise and Jitter for a high speed fanout chip

Question asked by WadeZhang on Feb 26, 2016
Latest reply on Mar 29, 2016 by JLKeip

Hi guys,

We are designing low phase noise distribution links.

The question raises on how does the additive phase noise of a fanout chip varies with input frequency changes.

 

If considering PLLs, DDSes or Dividers, we know the output phase noise has a 20xlog10 (D/N) rule to the input phase noise (although PLL is a bit more complicated than that).

 

However, when considering fanouts/mux/distribution devices, we notice the phase noise of such chips isn't consistent. For example, the additive phase noise of AD9525 @ 122.88MHz, 1475MHz and 2949MHz increases in a unclear way.

It makes it difficult to predict the (additive) phase noise of the certain chip when working at a frequency we want. As a consequence, it is difficult to choose the medium frequencies of a distributed multi-loops PLL in our system.

 

The following graph shows the additive phase noise of AD9525, AD9520 and ADCLK950 at different frequencies, according to the datasheet.

Is there anyone familiar with such problem? Or article/application note? Or the only way is to test each individual chip at each individual frequency? 

Phase Noise of Clock Sources Normalised to 1GHz and Distribution Chips Tested @ Different Frequency.png

Thanks a lot.

Best regards,

Weida

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