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AD9271_Penalty for low encode rate mode?

Question asked by Yan on Jun 30, 2011
Latest reply on Jul 8, 2011 by Yan

Has anyone come across this ADC chip before? I will like to have some advices on using this chip at a sampling rate that is lower than the typical minimum 10 MSPS for this chip.


The datasheet of this device mentions on the Page 32 that "The lowest typical conversion rate is 10 MSPS, but the PLL can be set up for encode rates as low as 5 MSPS via the SPI if lower sample rates are required for a specific application."


I also find the memory map register that enables this mode. However, before I start doing so, I will like to know what may be the drawbacks of using this chip at the low encode rate mode, which is not discussed in the datasheet.