Here is my general idea let me know if this is valid based on the architecture (working with a SoC running Linux and FMComms3)...
1) Generate data in software
2) Pass data from software (GRC/C++) to FPGA fabric
3) FPGA splits data and modulates I and Q (obviously many sub steps)
4) Output I and Q back to GRC/C++ where it is passed to the iio library block
5) Interpolating in AD9361
6) Moving to carrier frequency in AD9361
Am I assuming anything invalid wrt AD9361?