I'm working with a customer who is seeing issues when they port from the FMC-DAQ2 ADI reference design to a new version of Vivado. See customer's information below:
We are using a FMC-DAQ2 board and the ZC706 Xilinx Eval board to try to read ADC data from the DAQ2 board.
We have use the ADI reference design 2015_r1 version of the logic, built it using Vivado 2014.4.1 for the Zynq board and using the ADI version of the linux kernel and loaded the ZC706 board and was able to get data out from the ADC.
Then, we ported the design to Vivado 2015.4, removed all the blocks except for the blocks related to the AD9680 (the ADC on DAQ2 eval board), built the logic and using the Xilinx version of Linux, with patched drivers for the ADI related blocks and from chipscope, we are observing that the JESD cores is toggling in and out of sync.
I cannot figure out why the JESD core is not syncing with the ADC.
The rx_sync line of the JESD core oscillates at what looks like to be 88 clock cycles period (from 250 MHz) clock. Which means it's sync for 176 ns and then loses sync for 176 ns, etc.
Thanks for your support,