Our customer used the EVK board + Audio Precision to test performance, EVB and AP sample rate are setting 48KHz,
the connection and schematic as below:
The ASRC0 and ASRC1 config as below:
But the AP performance testing result as below:
You can observe some noise in the waveform.
They are using external crystal for generating MCLK 12.288MHz, and they want DSP to have a I2S output to their another audio module, DSP is as a I2S slave; and used AP to generate I2S BCLK and LRCLK to this port and receive this I2S SDAT.
However, the AP receive from this I2S port is noisy. In theory, it should be ok to output I2S and select BCLK and LRCLK as output clock domain.
Would you help to confirm this?
It is very urgent that our customer need to confirm this design and release the new PCB.
Thank you very much!