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AD9361

Question asked by FreddyS on Feb 23, 2016
Latest reply on Mar 3, 2016 by tlili

 

Hello,

I have a question about the AD9361:

We are trying to sync two RFIC's (AD9361) together from phase point of view.

 

We are transmitting the same RF frequency on both chips and we set bit MCS RF Enable (Register: 0x001[D3]) to keep the RF LO dividers ON in Alert Mode.

 

The AD9361 Tx and Rx PLL are always ON. (Register:  0x015[D2] = "1")

 

When both AD9361 chips are in constant Tx Mode.

 

We observe the sum of both Tx channels on a spectrum analyzer (using a combiner) we can see that the sum signal power is OK.

 

When we toggle both AD9361 chips from Alert to Tx, Tx to Alert, Alert to Rx, Rx to Alert using SPI commands (TDD normal operation).

 

We observe the sum of both Tx channels on a spectrum analyzer (using a combiner) we can see that the sum signal power has a very low frequency power fluctuation.

 

It looks like the phase of the AD9361 is changing when we toggle it in TDD mode.

 

Even if we use MULTI-CHIP SYNCHRONIZATION using an external Sync signal to both AD9361 chips we get the same very low frequency power fluctuation in TDD mode.

 

My question is what is causing this phase change when we work in TDD Mode ?

Thanks

Freddy 

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