In our application we have to sweep two PLLs over multiple frequencies. The absolute phase offset of both PLL-Outputs with respect to the reference should remain constant or at least predictable over all Frequency sweep. Unfortunatelly we are fixed to the HMC830
PLL and it is not possible to use other PLLs with phase sync function. The difference is in Seed value, that can be programmed to 4 init values only. Is it possible to reach the phase sync using this PLL?
According to this thread https://ez.analog.com/message/214063#214063 it will be not possible to zero the random phase offset due to the poor SPI-timing. According to the application I have a couple of opened questions I would like to adress to the forum members
- Is there any solution to sync the register writes of both PLLs or is it an intern problem of the PLL-Structure
- Is one of the solutions mentioned in ADF4350 Phase Resync possible to adress this issue?
- Sync SPI SEN to the reference using flipflop
- Use Chip Enable to reset the register states of both PLLs at the same time
- Will integer mode of operation change anything on the timing requirements?
Another out of scope question I cannot find an answer is why the exact frequency mode necessary condition for the phase tuning in the HMC835 PLL is.
Thank you for your response