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Queries about AD9119/9129

Question asked by WayneQ on Feb 22, 2016
Latest reply on Mar 4, 2016 by larrywelchusa

Hi, there


We are planning to operate the DAC with the sampling rate of 2.7 GHz and in second nyquist using Mix mode.



1) So we would like to know whether the part is capable of supporting instaneous bandwidth of 1 GHz (1.5 GHz to 2.5 GHz)


2) The DAC will be interfaced with Xilinx Ultrascale FPGA with LVDS operating at 675 MHz in DDR mode (1350 Mbps). The Xilinx FPGA claims the max LVDS data rate of 1400 Mbps. Do you anticipate any issues in this configuration ?


3) Required power flatness within 1GHz bandwidth is +/-1 dB. Can this be achieved ?