I am currently starting to work with an AD9361 (on AD-FMCOMMS3-EBZ) on a FPGA development board, using the ADI driver which I customized lightly ( AD9361 Device Driver Customization [Analog Devices Wiki] )
I am confused with the clocks configurations and as I can not find the answer I am asking for help here.
My setup is composed of a sine generator on the FPGA, two RF boards an oscilloscope and a signal analyzer.
I need FB_CLK and DATA_CLK's frequencies to be 40 MHz but I measure the DATA_CLK at 20 MHz. Furthermore, the sine's frequency is twice as low as it should be (4,85 MHz instead of 9,9 MHz).
Here is the definition of the clock paths I entered in adi-fmcommms2.dti :
/* BBPLL ADC R2CLK R1CLK CLKRF RSAMPL */
adi,rx-path-clock-frequencies = <1280000000 320000000 160000000 80000000 40000000 40000000>;
/* BBPLL DAC T2CLK T1CLK CLKTF TSAMPL */
adi,tx-path-clock-frequencies = <1280000000 320000000 160000000 80000000 40000000 40000000>;
I noticed that if I change the value of the register 0x00A (01 instead of 02) both my frequencies (sine on analyzer and DATA_CLK on oscillo) become correct. The out_voltage_sampling_frequency is then equal to 80 MHz, which was an invalid argument when I entered it directly ( sudo cat out_voltage_sampling_frequency echo 80000000 | sudo tee out_voltage_sampling_frequency)...
The reported path evolve as well:
(BBPLL : 1280, DAC : 640 ; T2:320 ; T1: 160 ; TF : 80 : TXSAMP : 80 (MHz))
This register (0x00A) doesn't seem to be modified when I load the driver.
Which configuration should I set, and do I miss some configuration options ?