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ADAU1701 DAC clock driven from PLL or MCLK ?

Question asked by basreflex on Feb 21, 2016
Latest reply on Feb 29, 2016 by Brettcoupe

I have a ADAU1701 design with the MCLK driven from a dirty clock from a spdif receiver. this affects the noise floor of the DAC severely.

I hoped that I could clean up the DAC clock by decreasing the PLL loop filter bandwidth, assuming that the DAC clock is derived from the system clock (49Mhz), but can anyone conform this assumption ?

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