Dear developer, dear support,
I'm working on ZedBoard + FMCOMMS2 + AD9361. I started to develop our project on the basis of HDL reference designe and No-OS driver of ADI. For HDL design, I removed everything unnecessary in our project and I saved only AXI-interconnect, iic_main, iic_fmc, i2c_mixer and I/O, HP and GPIO. Morever, I added a HDL IP of a modulator/demodulator configured in 4PSK modulation with 40 MSps data-rate and 5 MHz as bandwidth (2.5 MHz in base band). The IP module is able to generate PRBS-11 test pattern and to measure BER. If I configure the IP, via AXI4-Lite, to close its tx and rx path, it work properly and the demodulator is synchronized, the data are running and the BER is zero. I'm using FMCOMMS2. If I open internal loopback and I send generated data to tx path of AD9361 and I close external loopback with rx path using SMA-SMA connector, it seems not working. The demodulator is not synchronized. The system is configured as reported in the attached section of the main file. In particular I'm using 2rx2tx configuration, as later I'll have to instantiate 2 IP. At the momemnt, I'm using tx1 and rx1 (TX1A and RX1A closed in loopback). The tx and rx path are configured following your previous suggestion in order to substain a 40MSps data rate and CLK_OUT is a division of ADC_clock (ADC_clock is 320 MHz and CLK_OUT = ADC_clock/8 = 40 MHz), and it is used for reference clock in BBP. The RF bandwidth is 5 MHz. The two FIR filter is identical and are two LP filter with Fs=40 MHz and cut-off freq 2.5 Mhz in baseband to have 5 MHz in RF. The main doubts are related to TXNRX and ENABLE pins and the level of signal in rx and tx path. In the original reference design TXNRX and ENABLE were driven by HDL block design. In our design these two pins are not included. And in the software are considered only setting in the init function
/* ENSM Control */
0, //ensm_enable_pin_pulse_mode_enable *** adi,ensm-enable-pin-pulse-mode-enable
0, //ensm_enable_txnrx_control_enable *** adi,ensm-enable-txnrx-control-enable
Is it correct? If I monitor the ENSM status register I can see the ENSM is correctly in the FDD mode state. The four registers have the following values:
reg 0x13 = 0x01 (FDD mode)
reg 0x14 = 0x28
reg 0x15 = 0x04
reg 0x16 = 0x
reg 0x17 = 0x1A
Is it enough to assert the ENSM is correctly configured?
Furthermore, I did not understand how to set the same gain factor for tx and rx path. If I send to DAC the generated data, how can I sure to have the same level of the signal to the ADC output (or better at the end of rx path)?