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ADCLK846 Single Ended Clock Input

Question asked by test1 on Feb 18, 2016
Latest reply on Feb 19, 2016 by test1



I was hoping someone could help clear up my confusion on the ADCLK846.


We are planning to input a 1.3Vpp clock and having the ADCLK846 configured in single ended operation. Is it necessary to bias the clock to go from 0 to +1.3V, or can we leave it as -0.65V to +0.65V?


My confusion lies when looking at Figure 31 on page 14 of the datasheet which ac-couples a 1.8CMOS clock to the positive CLK input and GND to the negative CLK input. Wouldn't this violate the maximum requirements described as -0.3V to 2V for the CLK input (Table 5 on page 6) because the 1.8Vpp sinewave having DC blocked would actually swing from -0.9V to +0.9V, violating the lower limit?