How do I start the SHARC+ core after a secondary boot load?
This is the process;
2. ARM boots (ROM loader) itself, loads SHARC0 and SHARC1, both held in reset.
3. ARM releases SHARC0 from reset.
4. SHARC0 loads SHARC1 L1 from SFLASH (loader file).
5. SHARC0 signals ARM to release SHARC1 from reset.
6. ??? - what's next - ???
This is what I have done that is _NOT_ working; ARM sets RCU_SVECT2 to the address (0x001C0A06) in the first block of the loader file and calls adi_core_enable(ADI_CORE_SHARC1).