MaheshN

In UART FIFO mode, will the UART receive the data only in exact multiples of the Rx Trigger level?

Discussion created by MaheshN Employee on Feb 18, 2016

Say a packet received is 29 bytes, does the user need to know how many bytes are expected and adjust the RX Trigger level setting accordingly?

 

No. Say that you have set the trigger level to 8. You should receive 3 RX Buffer full interrupt and 8 bytes are read in each interrupt. Now the question is about the extra 5 bytes. Note that you will never receive a RX Full interrupt as the byte count (5 in this case) is lower than the trigger level set (8). UART uses a timeout to solve this problem.

This UART design confirms to the UART 16550 protocol and for this protocol , the Rx FIFO timeout occurs  if all of the following conditions exist:

  1. At least one character is in the FIFO
  2. The most recent character was received more than four continuous character times ago. A character time is the time allotted for 1 START bit, n data bits, 1 PARITY bit, and 1 STOP bit, where n depends on the word length selected with the WLS bits in the line control register (LCR).
  3. The most recent read of the FIFO has occurred more than four continuous character times before.

When the Rx Time out happens, the users are expected to read the RX FIFO byte count and read the receive buffer 'byte count' number of times. So irrespective of the trigger level set, whenever the Rx FIFO time out happens, the receive buffer should be read the RX buffer 'n' times to avoid losing the data (where ‘n’ = RX Fifo byte count)

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