I am using a custom board with cache enabled and 8MB of external SDRAM. What is the best way to subdivide the CLPBs pages? Initially I thought I would create 16 * 512KB pages. After realizing that there is no macro for PAGE_SIZE_512KB, I assumed that only the following page sizes are supported:
#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
Would it be best to create 8 x 1MB pages? Or should I create 2 x 4MB Pages?
I should also mention that I want one page to be set as CPLB_DNOCACHE, so that I can DMA into it without having issues with Cache WB mode.