I'm designing a system around the AD9434, and I find the datasheet (rev. B) to be unclear on some points, and I would appreciate it if someone could help me understand it better.
The AD9434 is a 1.8V device, for both the analog and digital parts, as clearly shown in the "Pin Function Descriptions" section.
The datasheet also states that the CML (common mode) voltage level is 1.7V, which usually means that the VIN+ and the VIN- should swing around 1.7V. The datasheet doesn't state it exactly like that, but it says that the CML pin "provides a reference for the optimized internal bias voltage for VIN+/VIN−", and also shows the CML voltage biasing an AD8138 amplifier, and the datasheet for the AD8138 amplifier makes it clear that the analog signal will swing around the CML voltage level, stating "For example, 1 V dc on VOCM sets the dc bias level on +OUT and −OUT to 1 V". A few other places in the AD9434 datasheet reinforce this interpretation, so I'm convinced that I'm understanding it correctly. This is not surprising, as I've seen this many times before.
The datasheet of the AD9434 also states that the VIN signal can swing up to 1.6Vpp, so 0.8V above the CML voltage and 0.8V below the CML voltage (if CML voltage is used like in "Figure 41. Differential Input Configuration Using the AD8138" of the AD9434 datasheet).
All this makes sense to me except for a CML voltage level of 1.7V, because a swing of +/- 0.8V around 1.7V will clearly exceed the 1.8V limit of the device. The "ABSOLUTE MAXIMUM RATINGS" section makes it very clear that VIN+ and VIN- cannot exceed the 1.8V of AVDD by more than 0.4V, although I'm pretty sure that 0.4V is just the ESD diode voltage drop and that for the ADC to deliver its full potential VIN should not exceed 1.8V at any time.
Can anybody please explain how such a thing will work? Why "Figure 41. Differential Input Configuration Using the AD8138" can work with a CML level of 1.7V from the AD9434 into the AD8138 and with an input signal that is 1Vpp?