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AD7606 time cycle DoutA

Question asked by jazcarretao on Feb 17, 2016
Latest reply on Feb 19, 2016 by jazcarretao

Dear community,

 

I am working with AD7606 to interface an array of 8 microphones with an FPGA through an SPI communication protocol.

 

I am concerned about the maximum cycle time possible for the conversion. Those are the datasheet requirements:

Time_Cycle.PNG

However, I am planning to use just DoutA line, thus the throughput rate will be lower. Here is the problem, I find the timing specifications very tight when using just DoutA and with a SCLK of 12 MHz I cannot fill the requirements of the table above. I am not sure if the table gives a cycle time limit when just using DoutA.

 

My question is simple: which is the maximum cycle time when using the following parameters?

 

My parameters:

- Vdrive = 3.3 V

- just using DoutA.

- SCLK = 12 MHz

- fs = 200 kHz (wondering if I should use 50 kHz better for my audio application).

 

Please, if you need further information do not hesitate to ask me.

Thanks for your help,

Best regards,

Juan

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