I am using the AD9122 DAC and I am seeing strange results.
We are using the DAC in the FIFO rate synchronization mode, reg 0x10 = 0x88. We are driving the DAC using a Xilinx Virtex 6 part.
We are running the DACCLK at 1GHZ, and the DCI is at 125 MHZ (an interpolation of 8). We have the Sync Clock repeat every 8 DCI clock cycles just like figure 49 of the datasheet. We have several different boards, and to get a clean signal out of the DAC, we need to vary the delay of the SYNC line differently for different boards. When the signal is not clean, we can see a jump on an o-scope that appears to be related to the 1 GHz clock (1ns jumps). And some boards need to have a delay of 0 ns between DCI and the DATA bits, and some need 125 to 250 ps of delay.
And we ran this in another configuration where the DACCLK is 213 MHZ and the DCI is at 106.5 MHZ (an interpolation of 2). We did not see this behavior.
It feels like the SYNC line is somehow connected to the DACCLK, but I cannot see how in the datasheet.
We need to run the DAC with the 1GHZ line and have the delay be the same for all boards. We are using LDVS drives out of the FPGA for all the DATA,DCI and SYNC lines. We do not have extra termination resistors on the board for these signals.
The termination for the DACCLK on my board matches exactly what was done on the AD9122-M5375 board. But the REFCLK on our board is tied directly to the FPGA with no termination on the board.
Terminating the DACCLK really close to the DAC did not help. Now suspecting jitter on the DACCLK itself. Measured about 500 ps worth. Trying to clean it up in the FPGA.
UPDATE 2 and RESOLUTION***
It was jitter. Didn't need the termination resistor. Took the REFCLK from a cleaner source within the FPGA. Seems to have fixed the problem.