We have encountered the following issue wit BF707 processor
If our generated LDR file contains sections that are not aligned at 4 byte boundaries
loading the above-mentioned LDR file (from both SPI-flash and UART) fails.
Is it normal?
We use the following workaround:
we add a prefix to output file name in project settings.
Output file name is added to a section of the output file itself.
So it may correct the misaligned sections issue.