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AD9834 : output settling at exiting from power-down mode

Question asked by ysuzuki on Feb 16, 2016
Latest reply on Feb 17, 2016 by musach

Hello,

 

I have a question from our customer about the delay of AD9834 when exiting from power-down mode.

 

Attached files are waveforms at exiting from power-down.

I captured these trace(wavefome) using EVAL-AD9834EBZ.

 

COMP_0_01uF-1.png : used default decoupling capacitor(0.01uF) to COMP Pin

COMP_4700pF-1.png : used 4700pF to COMP Pin

 

The traces are:

  Green : wavefomr of SLEEP Pin

  Read  : waveform of COMP Pin

  Blue  : waveform of IOUT Pin

 

 

It looks like that the settling time of IOUT is influenced by the COMP pin decoupling capacitor size.

 

Q1. The IOUT output signal appear at about middle point of the transition of COMP pin voltage. Does AD9834 disable the output until the bias voltage come close to final  bias voltage ?

 

Q2. Could you please explain me the internal sequence(AD9834) at exiting from Power-down mode ?

 

 

Best regards,

ysuzuki

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