why input data in sys_wfifo ip in block design in fmcomms1 is 32 bit but output data is 64 bit?
Thanks, now you can see why the bus width difference is. In any design, it is the bandwidth that you need to account for. It is however, possible that higher bus width will be a problem with handshake interfaces, but none of these interfaces support any sort of handshake.
What are its input and output clock frequencies?
List down the rates (not just bus widths) and you will understand.
m_clk is input clk that connect to adc_clk :
and s_clk is output clk that connect to fifo_wr_clk :
but i don't know what is the value of adc_clk and s_clk?
You are showing me some connections-- you need to find the frequencies based on how you setup things and the sampling rates you are running things with.
input clk data in sys_wfifo ip( adc_clk) is 250 MHz and output clk data(adc_dma_clk) is 125MHz .
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