We are using the AD7785 on an SPI bus with two other ADCs. Our desire is to initiate a conversion with a write to the device, and during the AD7785 conversion time (which could be long depending on the final selection), we would like to use this bus to communicate with the other devices.
In the AD7785 spec Digital Interface section, Figure 17 (p23) shows a timing diagram for single conversion mode. It shows the CSn line held low for the entire conversion cycle. On the other hand the timing diagrams on page 7 show CSn being used a chip select for descrete read and write operations.
Is it a requirement to hold CSn low during the entire conversion?
If not and CSn can be returned high,
a) is the DOUT / RDYn pin tri-stated?
b) could transitions on SCLK And DIN possibly affect the data conversion (or are they sufficiently isolated for this not to be a concern)?