The HMC832.pdf RevA page 29&30 states:
1 ) At power-up, it is required that both SEN and SCK lines are initially held low, and
2) The first rising edge occurs on the SCK line before any rising edges occur on the SEN line.
It then provide this warning:
If the first rising edge occurs on the SEN line before it does on the SCK line the HMC832LP6GE SPI interface does not function.
I do understand that point (2) is critical, after all the datasheet specifically states that if we violate this the SPI interface will not function
However I am not so sure about point (1).
Our Control Logic Implementation
Currently our FPGA powers up with SEN high and SCK high
Once the FPGA has been programmed the SEN stays high and the SCK transitions low.
They both stay in this state until a PLL write is executed.
At the start of a write SEN is driven low and the SCK goes thru all 32 clock periods before SEN goes high.
This sequence honours point (2) above, but not (1)
- If we keep the current logic implementation described above, would it violate the serial port initialization?
In Summary then how critical is point (1) above ??.