I use an AD9228 ADC with an FPGA and configure the SPI pins with external resistors to come up in the non-spi mode because during system power on, the FPGA is not initialized and cannot drive the SPI pins itself. After the FPGA has been initialized, we send commands to the ADC through SPI. My problem is that it seems the commands are not accepted by the ADC.
I send the command to put out checkerboard test pattern on digital pins: 0x00d04, but the digital values I experience on the deserializer in the FPGA are still regular digital words corresponding to changing analog values on the ADC input. Changing the digital word coding from offset binary to 2-complement: 0x01401 has no effect on the output word.
I have been scoping the csb, sdio and sclk signals on the pins of the ad9228 and they are coming through. We use 1.8V for all power to the AD, and level shifters on the connection between FPGA and AD. The SPI signals at the AD are all 1.8V range.
My SPI clock speed is 6.25 MHz and the rising edge of the SPI clock is happening in the middle of the SDIO data. A problem may be that the CSB signal rises before the SCLK falling edge. The minimum timing of 2 ns from rising edge SCLK to rising edge CSB is not a problem at this low speed.
Question is if the falling edge of the SCLK also must happen before the rising edge of CSB.
Question is if the ad9228 comes up in normal operation non-spi mode can be programmed by SPI at a later time after power up.