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EZKIT 21469: TWI Communication Runs out of sync

Question asked by LordBIX on Feb 8, 2016
Latest reply on May 13, 2016 by Jithul_Janardhanan

Dears,

 

i am running a communication interface with high frequent TWI communication for LED drivers. VDSP 5.

 

For some reason, i run almost predictable into TWI communication issues after around 200 TWI calls in around 3 seconds.

 

TWI runs in asynchronous FAST mode. Its build based on the thermo controller TWI example.

 

Paramters:


#define NOS_TWIMCTL            (TWIFAST) // Fast Mode with restart

#define NOS_TWI_CLKDIV          25

#define NOS_TWI_CLKHI          8

#define NOS_TWI_CLKLO          17


The write cycle calls back the interrupt normal like this:

Cycle 1 (Adress Cycle):  

--TWIIRPTL0x00000040
--TWIMSTAT0x000001C1
--TWISSTAT0x00000000
--TWIMCTL0x00000041
--TWIMADDR0x00000060
--TWIIMASK0x00000050
--TWIFIFOCTL0x00000010
--TWIFIFOSTAT0x00000000

Cycle 2(Write Register):  

--TWIIRPTL0x00000040
--TWIMSTAT0x000001C1
--TWISSTAT0x00000000
--TWIMCTL0x00000001
--TWIMADDR0x00000060
--TWIIMASK0x00000050
--TWIFIFOCTL0x00000010
--TWIFIFOSTAT0x00000000

Cycle 3 (Write Content of Register 1 byte):  

--TWIIRPTL0x00000010
--TWIMSTAT0x00000100
--TWISSTAT0x00000000
--TWIMCTL0x00000000
--TWIMADDR0x00000060
--TWIIMASK0x00000050
--TWIFIFOCTL0x00000010
--TWIFIFOSTAT0x00000000

 

After the several cycles there seems to be an FIFO Issue, which i can't distinguish its coming from. The results look like this:

Cycle 1 (Adress Cycle):  

--TWIIRPTL0x00000010
--TWIMSTAT0x00000000
--TWISSTAT0x00000000
--TWIMCTL0x00000000
--TWIMADDR0x00000060
--TWIIMASK0x00000050
--TWIFIFOCTL0x00000010
--TWIFIFOSTAT0x00000001

Cycle 2(Write Register):

  

--TWIIRPTL0x00000040
--TWIMSTAT0x000001C1
--TWISSTAT0x00000000
--TWIMCTL0x00000041
--TWIMADDR0x00000060
--TWIIMASK0x00000050
--TWIFIFOCTL0x00000010
--TWIFIFOSTAT0x00000001

Cycle 3 (Write Content of Register 1 byte):

  

--TWIIRPTL0x00000030
--TWIMSTAT0x00000108
--TWISSTAT0x00000000
--TWIMCTL0x00000040
--TWIMADDR0x00000060
--TWIIMASK0x00000050
--TWIFIFOCTL0x00000010
--TWIFIFOSTAT0x00000003

 

Now my questions:

  • What does that FIFOSTAT Register Status means for my situation..
  • What does the IIRPTL register status means?


I am not getting a clue based on the HW manual, how this issue can prevented. My assumption, that this is caused by an additional write to TXTWI8 i could not verify in my code. It seems as well, as the behavior gets better with running the interface on fast mode.

 

In general the code has NO delays while setting all TWI registers. The read / writes are executed with a self initiating IRQ to prevent CPU in dead zones. Thats why the code is fairly complex and really hard to debug.

 

Any idea is appreciated, as i am trying to tackle this issue since 4 weeks now.

 

Thanks

 

/Marco

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