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AD9361 clock setup

Question asked by g.dallemura on Feb 8, 2016
Latest reply on Feb 10, 2016 by DragosB

Dear developer, dear support,

I'm working on ZedBoard + FMCOMMS2 + AD9361. I'm new with AD9361. (I'm new with support community, sorry if the discussion is not in the correct section) I have to develop a project with this transceiver and I a started with the ADI reference design, HDL for FPGA part and No-OS for software/driver. For HDL I started with the original one and I modified it according to the requirements of the new project. Especially, I removed the ADC and DAC part, the DMA and VDMA management and I added an IP for data modulation/demodulation. This IP communicate to PS of Zynq via AXI-Lite. In the software no-OS (baremetal application), I modified the software accordingly: I removed driver for ADC - DAC. Now I created my application and I'm able to communicate via AXI between PS and PL, I configure correctly the IP, and the init of AD9361 with ad9361_init seems to be accomplished successfully. But I'm not able to configure correctly the rate of the various clock of AD9361. I need the CLK_OUT = 40 MHz (used as a reference clock in the FPGA design) and the ADC_CLK = 160 MHz in order to have a 40 MSps in LVDS configuration. I have 1 rx channel and 1 tx channel. I'm using in loop-back configuration with a SMA-SMA cable between the TX1A (J112) and RX1A (J110). I set the REG_BBPLL in the following way:

#define CLKOUT_ENABLE     (1 << 4) /* CLKOUT Enable */
#define DAC_CLK_DIV2     (1 << 3) /* DAC Clk div2 */
#define CLKOUT_SELECT(x)     (((x) & 0x3) << 5) /* CLKOUT  Select<2:0> */
#define BBPLL_DIVIDER     (((x) & 0x2) << 2) /* BBPLL Divider <2:0> */

in order to have CLKOUT=ADC_CLK/4. Even if BBPLL_DIVIDER is not used in the init.

As init parameters, I used the default AD9361_InitParam default_init_param except for the following part:

 

/* Base Configuration */
0,//two_rx_two_tx_mode_enable *** adi,2rx-2tx-mode-enable

 

/* Rate & BW Control */

{720000000, 160000000, 80000000, 40000000, 40000000, 40000000},//uint32_t rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies

{720000000, 160000000, 80000000, 40000000, 40000000, 40000000},//uint32_t tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies

 

CLKOUT_ENABLE,//clk_output_mode_select *** adi,clk-output-mode-select


In this way, I figured to set BBPLL as a 720 MHz clock, the ADC and DAC clock 160 MHz (for LVDS config) that sustain a 40 MSPS. Is it correct? But if I check the CLK_OUT frequency in P202 test-point I find the frequency is 45 MHz, then I can think the ADC_CLK is 180 MHz. In fact, if in the consolle I get tx_samp_freq? and rx_samp_freq? i receive 45 MHz. If i set rx_samp_freq=40MHz the CLK_OUT measured is 80 MHz. Is it possible? The ADC_CLK should be 320 MHz? At the init, the register 0x00A is set to 0x72, I'm not able to set the D3 bit to 1, and after the set command rx_samp_freq=40MHz 0x00A register is 0x79. Is there something wrong in this configuration? How can i set the ADC/DAC clock is 160 MHz and consequently the CLK_OUT = 40 MHz? Or I have just to set the register 0x00A to 0x12 (just to have buffered version of DCXO 40 MHz)? What is the correct step or procedure to correctly initialize the AD9361 with the desired rate?


Thank you in advance for your attention,

Gab

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