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Question asked by thotho on Feb 6, 2016
Latest reply on Feb 24, 2016 by thotho

Hi, I need interface the ADC9625 with a FPGA. When I implement the JESD204B module with ISE automatically is generated a verilog code. I try to modify it to use for my purpose, but it doesn't work. Can I know how modify it to use or where I find a VHDL or verilog code for my purpose?


Best regards.