I am starting the design of a frequency synthesizer with the HMC 778 PLL. As a reference, I am using one design already done with the HMC 767.
I try to understand the loop filter already done in that design. Unfortunately, the results does not fit well with the PLL theory.
I don't know if the filter is bad, the simulation (on ADsimPE) is wrong because of my fault or the previous engineer has decided to do the filter in this way by some reason. Could anyone help me please? I can send you the .wxsch file and more information in PM.
Many thanks in advance, I have no more ideas!