i wanted to update my reference design for the fmcomms2 and zedboard. I downloaded the 2015_r1 branch and be able to run synthesis and implementation. To enable the UART0 i followd the instruction by Howto export Zynq peripherals(I2C, SPI, UART and etc) to PMOD connectors of ZedBoard using Vivado 2013.4 | d9 Tech Blog (to the point where they update the constraints in zynq module). I ran the synthesis and implementation to check the I/O port to define the PINs for EMIO UART0. Unfortunately UART0 seems not to be implemented, so there is no entry in the I/O Port list of the implementation.
Do you have any idea to solve this issue. I think there might be an issue with the system_top.v. When i update the HDR wrapper the UART0 is displayed in it but when i'am looking for UART0 in system_top there is none. Do i have to update it in any way or do i need to insert the UART 0 manually?
Thanks and regards