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ADV7513 PLL Lock Period

Question asked by Geoff65 on Feb 3, 2016
Latest reply on Jun 13, 2016 by MikeOC

We are currently developing a video system which includes the ADV7513 (165 MHz High Performance HDMI Transmitter).

 

The ADV7513 has been successfully configured to operate in CEA-861D format No.30 (ie. 1440 x 576p @ 50MHz in 16:9 aspect ratio).

 

The problem is that there is a very long delay between configuring the ADV7513 and when the video output from the ADV7513 is sent out to the HDMI display screen.

 

We can find no mention of any measurement (or estimate) of the time taken for the ADV7513 PLL to achieve lock - in the ADV7513 datasheet, or in the ADV7513 Hardware User's Guide, or in the ADV7513 Programming Guide.

 

Is there any specification as to how long the ADV7513 PLL should take to achieve lock ?

 

An experiment run on our prototype system seems to indicate that the PLL is taking upwards of 200 milli-seconds to achieve lock.  Is this correct?   This measurement was achieved by timing from the last configuration data being written to the ADV7513 (via I2C) and when the PLL Lock status bit (Reg 0x9E bit 4) is set.

 

Note that the prototype system has a highly stable voltage being provided to the HDMI PLL Vdd (pin 12) and there is a 200 milli-second delay between power being provided to the ADV7513 and when the first I2C command are sent to the ADV7513 - as per the Hardware User's Guide.

 

As a result we have a delay of 200msec (delay to allow Power to stabilize), 1.4msec to send all I2C configuration to the ADV7513, and then 200msec for the ADV7513 PLL to achieve lock.   The HDMI screen has some small delay to synchronize to the output video signal - so there is a noticeable delay of almost half a second between system reset and the display appearing on the HDMI screen.

 

Please advise as soon as possible.

 

Thank you.

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