Dear Analog Devices!
I'm using the AD9508 Clock Buffer to create two LVDS clocks of 20MHz and 40MHz out of an LVDS clock signal with 40MHz.
As this is fixed, I routed the "Pin strapping to program on power-up", as described on page 26 in the datasheet, where:
IN_SEL (Pin 23) -> 10k to 3.3V (Differential input)
PROG_SEL (Pin 15) -> 10k to 3.3V (Pin programming)
S0 -> 820 to GND
S1 -> 1.8k to GND
S2 -> 820 to GND
S3 -> 820 to GND
S4 -> 820 to 3.3V
S5 -> 820 to 3.3V
- all outputs should be LVDS, and
- OUT0 is divided by 1 (feeds FPGA, 100Ohm terminated)
- OUT1 is input clock divided by 2 (feeds ADC over 100nF decoupling caps on both lines, after the 100Ohm Termination)
The 40MHz clock on OUT0 can be measured when the 100Ohm termination resistor is placed on the PCB, like it is expected.
But the 20MHz LVDS clock ad OUT1 can not be measured. Instead, the chip delivers a signal that is "nearly DC" at 1.8V with small rectangular steps to 1.6V every 25ns. These 25ns are equivalent to 40MHz (1/(25e-9) = 40e6).
From my understanding of the datasheet, no further programming or SYNC-Toggle should be necessary to let the AD9508 just give those expected outputs.
I added the schematic part of the AD9508.
Did I miss something in the datasheet? Do you have an idea what could be mistaken?